UFS V5 IT: Reducing Repeated NGBin 19/109 Yield Excursions Through Wafer-Edge Pattern Analysis

Overview

UFS V5 IT, an anonymized internal product/generation code for a UFS product based on 5th-generation V-NAND, repeatedly showed abnormal NGBin 19 and NGBin 109 yield excursions during MBT testing from 2020-07 to 2021-W12.

The issue appeared in three distinct excursion windows: 2020-07 to 2020-08, 2020-10 to 2021-01, and 2021-W11 to 2021-W12. The periods between these windows were observation or post-action periods, not part of the excursion windows. The repeated excursions triggered abnormal handling and WIP hold, affecting production flow and manufacturing cost.

After consolidating all three excursion windows and observation periods, the key pattern became clearer: affected chips were more likely to come from wafer-edge regions. Fab-side process adjustments were then applied, reducing the combined NGBin 19/109 defect rate by approximately 3,007 ppm, with an estimated monthly cost saving of about ¥3.48M.

Terminology

• UFS: Universal Flash Storage, an embedded flash storage product type.
• UFS V5 IT: An anonymized internal product/generation code for a UFS product based on 5th-generation V-NAND. The internal code is retained as written and is not expanded as a public acronym.
• MBT / mBIST: Memory Built-in Self Test, a long-duration memory test process used to screen NAND characteristic defects.
• NGBin: A negative-bin / failure-bin category used to classify test failures.
• NGBin 19: Full Erase Fail.
• NGBin 109: Full Block Read Fail.
• EDS: Electrical Die Sorting, the wafer-level electrical test used to screen dies before backend assembly.
• Wafer map: A spatial map of chip-level results across a wafer, used to identify location-based yield patterns such as center, edge, ring, or random distributions.
• CVD: Chemical Vapor Deposition, a fab process used to deposit thin-film layers.
• TEOS: Tetraethyl orthosilicate, a silicon oxide precursor used in semiconductor deposition processes.
• Spotfire: Visual analytics software used here for yield, bin, wafer, and defect-pattern analysis.

Problem

Starting from 2020-07, UFS V5 IT repeatedly showed concentrated NGBin 19 and NGBin 109 failures during MBT testing.

The same two failure bins increased across three distinct production windows. These excursions triggered abnormal handling and WIP hold, disrupting production flow and creating direct cost pressure.

The challenge was to determine whether the repeated failures came from backend test noise, backend equipment concentration, wafer-level characteristics, or upstream fab process contribution.

Data Used

• Monthly and weekly UFS V5 IT production input volume
• Monthly and weekly yield trend
• NGBin 19 ppm trend
• NGBin 109 ppm trend
• Combined NGBin 19/109 defect-rate trend
• MBT retest results
• Equipment concentration check
• Wafer concentration check
• Wafer map distribution review
• Spotfire-based yield and bin visualization
• Fab-side EDS wafer-level test condition changes
• Fab-side CVD / TEOS process feedback
• Post-change defect-rate monitoring

Review Scope

• The issue repeated across three distinct windows, so a single-month or single-equipment explanation was not enough.
• The periods between excursions had to be treated as observation / post-action periods, not as part of the excursion windows.
• Retest results indicated that many failures were true defects, not simple false-fail cases.
• Early analysis did not show clear backend equipment concentration.
• The first two excursion windows did not show a simple wafer concentration pattern.
• Fab-side process contribution had to be investigated through cross-functional feedback rather than backend test data alone.
• The case needed to avoid treating backend yield loss as only a backend process problem.

Approach

The investigation moved from backend MBT symptoms to wafer-level and fab-side process correlation.

Investigation Focus

• Consolidated NGBin 19 and NGBin 109 trends across three distinct excursion windows.
• Separated excursion periods from observation / post-action periods.
• Compared input volume, yield, and ppm movement across monthly and weekly periods.
• Used visual analytics to review defect-bin trends and concentration patterns.
• Checked retest behavior to separate true defects from false-fail noise.
• Reviewed equipment concentration and confirmed no clear backend equipment concentration in the early excursion periods.
• Reviewed wafer concentration and wafer map behavior.
• Escalated repeated abnormality to fab-side teams for process feedback.
• Tracked fab-side wafer-level test condition changes and process-control adjustments.
• Reanalyzed the three excursion windows together instead of treating them as isolated events.
• Identified that affected chips were more likely to come from wafer-edge regions.
• Supported follow-up monitoring after fab-side CVD / TEOS condition changes.

Key Investigation Choices

Root Cause / Key Finding

The repeated NGBin 19 and NGBin 109 excursions were linked to wafer-level characteristics rather than backend equipment concentration.

After consolidating the three abnormal windows, affected chips were found to be more likely located near wafer-edge regions. This pattern supported fab-side review of wafer process conditions. Fab-side improvements were then applied, including CVD-related interlock timing adjustment and TEOS-related process delay/thickness adjustment.

Fab process changes are described only at the generalized process-control level, without exposing internal recipe details.

Corrective Actions

• Reviewed EDS wafer-level test conditions and related screening logic.
• Applied wafer-level condition changes to reduce downstream backend yield loss.
• Reviewed fab-side CVD process conditions related to the repeated abnormal pattern.
• Adjusted CVD-related interlock timing.
• Adjusted TEOS-related process delay/thickness condition.
• Continued monitoring NGBin 19/109 ppm after changes.

Methods & Tools

• Yield Excursion Analysis
• Defect Pattern Analysis
• Statistical Monitoring
• Factory Data Analysis
• Cross-Functional Feedback
• Cost Impact

Result & Impact

Combined NGBin 19/109 defect rate was reduced by approximately 3,007 ppm, with an estimated monthly cost saving of about ¥3.48M. Repeated abnormal handling and WIP hold risk were reduced, and the investigation connected backend MBT failures with wafer-level spatial patterns and fab-side process conditions.

Notes

• Repeated yield excursions across multiple windows should be analyzed together, not only as isolated OCAP events.
• Observation periods are important because they show whether an action produced temporary recovery or long-term stabilization.
• Retest behavior is important for separating true yield loss from false-fail or screening noise.
• Lack of backend equipment concentration does not rule out upstream process contribution.
• Wafer map and edge-pattern analysis can reveal fab-side mechanisms behind backend test failures.
• Yield improvement has direct cost impact, especially when high-volume production is involved.
• Backend quality data becomes more valuable when it can drive fab-side process feedback.