M.2 SSD DAS FET Burnout Root Cause Analysis and LI Process Improvement

Overview

DAS stands for Device Active Signal. In this M.2 SSD design, the controller GP21 signal drives the DAS FET, which controls the host-side LED interface. A current limiter and a 100 kOhm pull-up to 3.3V_lim are applied on the interface side.

During LI, or Label Attachment & Interface Test, intermittent DAS-related failures were observed. FET burnout was confirmed in 35.3% of DAS fail cases, and the PM9A1-family collected/confirmed FET burnout rate reached 7 ppm during the analyzed period.

The failure trend showed intermittent PPM spikes rather than a stable process baseline. Further analysis found vendor concentration, gold finger scratch and conductive debris, LI socket insertion risk, PCB/socket tolerance stack-up, and a limitation in the previous DAS Check logic. After countermeasures, the collected/confirmed FET burnout rate decreased from 11 ppm to 2 ppm with p-value < 0.001.

Terminology

• DAS: Device Active Signal, a signal used to control the host-side LED status and check connection/activity behavior through the controller and DAS FET path.
• FET: Field-effect transistor, the switching device used in the DAS-related LED interface circuit.
• LI: Label Attachment & Interface Test, a late-stage SSD process covering label/shipment-related checks, process-mix control, unique information writing, interface validation, hardware checks, and PHY/power-management tests.
• DAS Fail / 4502: An internal LI fail condition related to DAS behavior.
• 4590: An internal recognition/contact-related fail pattern used here as a monitoring signal for socket/contact abnormality.
• Gold finger: The exposed plated edge connector contacts of the M.2 SSD.
• 3.3V_EXT: External 3.3 V supply contact on the M.2 interface.
• LED contact: The host-side LED/DAS-related interface contact.
• CPK: Process capability index used to evaluate dimensional process capability and variation against specification limits.
• AVI: Automated visual inspection.
• PGM: Test program logic used in the SSD test process.
• CTRL: Controller, the SSD controller IC.

Problem

DAS FET burnout was observed on the DAS-related circuit. Confirmed samples showed burnt marks near the DAS FET area, solder-side abnormality around the affected circuit, internal chip burnout, and DAS fail or other LI fail-code patterns before final DAS fail classification.

Only 24% of FET-burnout SSDs had 4502 DAS Fail as the prime fail code, but approximately 75% had 4502 DAS Fail as the final fail code. This suggested that FET burnout could occur during repeated LI test cycles.

Because SSDs can be inserted and retested multiple times during LI, repeated socket insertion and removal became a key investigation direction.

Data Boundary

• FET burnout statistics are based on SSDs collected and confirmed as FET burnout cases.
• If some SSDs were shipped out and not collected for analysis, those cases may not be included.
• All rates in this case should be interpreted as collected/confirmed FET burnout rates, not absolute field occurrence rates.
• The public case uses generalized manufacturing context and omits real customer names, equipment IDs, internal report names, raw logs, and proprietary drawings.

Data Used / Data Signals

• DAS fail analysis result: 35.3% of DAS Fail cases confirmed as FET burnout
• PM9A1-family collected/confirmed FET burnout rate: 7 ppm during analyzed period
• Intermittent monthly PPM spikes, especially 2021-03, 2021-07, 2021-09, and 2022-01
• PCB vendor comparison: TLB 15.7 ppm vs TRIPOD and UMTC 0.7 ppm
• Prime vs final fail-code shift: 24% prime 4502 DAS Fail vs approximately 75% final 4502 DAS Fail
• Gold finger scratch and Au debris observations
• 3.3V_EXT-to-LED solder bridge reproduction result
• Previous DAS Check PGM logic and final_das_cnt behavior
• Before/after collected-confirmed FET burnout rate: 11 ppm to 2 ppm
• p-value < 0.001 for before/after improvement comparison

Approach

The investigation treated the defect as a chain rather than a single-cause issue. Repeated LI socket insertion and removal created wear risk on SSD gold finger contacts and socket contacts. Au plating wear could generate conductive debris near edge connector contacts, and conductive debris could bridge adjacent contacts to create leakage or an intermittent short path.

A 3.3V_EXT-to-LED short was confirmed as capable of inducing DAS FET burnout through reproduction. TLB PCB dimensional variation and socket keying tolerance stack-up reduced contact alignment margin, and lateral SSD shift during socket insertion increased the risk of contact overlap or shorting.

The previous LI DAS Check judged only DAS toggle count, so some FET-burnout SSDs could still pass if abnormal waveforms generated five detectable toggles. The combined mechanism created both a burnout generation risk and a screening escape risk.

Investigation Focus

• Monthly PM9A1 trend showed repeated PPM spikes in 2021-03, 2021-07, 2021-09, and 2022-01, indicating intermittent abnormal occurrence rather than a stable process-level baseline.
• TLB vendor PCBs showed a much higher collected/confirmed FET burnout tendency than TRIPOD and UMTC: 8,923.6k input at 15.7 ppm vs 9,835.4k input at 0.7 ppm.
• Gold finger scratch review connected repeated insertion/removal to Au plating wear and conductive debris risk.
• A 3.3V_EXT-to-LED bridge reproduced FET burnout during LI test, confirming that this short path could induce the damage.

PCB and Socket Process Review

• TLB North PCB A/C CPK values were lower than the target CPK: A CPK 0.85 and C CPK 0.80 vs target 1.33, indicating high dimensional variation risk despite being within specification.
• Router bit replacement interval was shortened from 2 m to 1 m of accumulated routing length, improving key notch-related dimensional stability.
• After PCB dimensional improvement, V CPK improved from 1.34 to 1.84 and X2 CPK improved from 1.43 to 2.37.
• LI socket keying feature width changed from 1.10 +/- 0.05 mm to 1.13 +/- 0.01 mm to reduce lateral SSD shift during insertion.

Screening Logic Review

• The previous DAS Check judged a 10-second window by final_das_cnt only, with pass at final_das_cnt = 5 and fail at final_das_cnt < 5.
• The previous logic did not verify LED voltage level, GP21 voltage level, voltage swing amplitude, VIH/VIL margin, final voltage level, leakage, or degraded FET behavior.
• After GEN4 9600APM CTRL board modification, the FET-burnout SSD could no longer generate five valid DAS toggles. final_das_cnt decreased from 5 to 1, resulting in Check DAS Fail.

Key Investigation Choices

Root Cause / Key Finding

The root cause was a chain: repeated LI insertion/removal increased contact wear risk; Au debris or contact overlap could create a 3.3V_EXT-to-LED short; the short could overstress the DAS FET; PCB/socket tolerance stack-up and lateral SSD shift increased the short risk; and the previous DAS Check could miss some damaged samples.

The previous DAS Check was count-based. It checked whether five DAS toggles were detected in the test window, but did not validate voltage-level quality, waveform margin, leakage, degraded FET behavior, or final voltage state.

The improved screening condition converted a previously LI-undetectable FET-burnout sample into a detectable Check DAS Fail.

Corrective Actions

• AVI inspection criteria improved to detect previously undetectable FET-burnout samples.
• CTRL board / DAS check condition improved to increase DAS screening sensitivity.
• TLB PCB dimensional capability improvement requested and confirmed through CPK improvement.
• Router bit replacement interval shortened from 2 m to 1 m to reduce tool wear.
• LI socket keying feature width changed from 1.10 +/- 0.05 mm to 1.13 +/- 0.01 mm.
• Socket lifetime management strengthened to reduce socket/contact wear.
• 4590-rate monitoring strengthened as an early signal for socket/contact abnormality.

Result & Impact

Collected/confirmed FET burnout rate improved from 11 ppm to 2 ppm, with p-value < 0.001. The investigation connected intermittent yield spikes, vendor concentration, mechanical contact wear, tolerance stack-up, DAS FET burnout reproduction, and LI DAS screening limitations into one root-cause and countermeasure framework. Supporting improvements included final_das_cnt movement from 5 to 1 on a FET-burnout sample after CTRL board modification, plus PCB CPK improvement from V 1.34 to 1.84 and X2 1.43 to 2.37.

Methods & Tools

• Failure Analysis
• Root Cause Analysis
• Yield Improvement
• Factory Data Analysis
• Statistical Validation
• Corrective Action

Notes

• Intermittent yield spikes require trend-based investigation rather than only lot-level reaction.
• Prime and final fail-code comparison can reveal whether a defect may be generated during repeated retest cycles.
• Mechanical contact wear and conductive debris can become electrical failure mechanisms in high-volume socket insertion processes.
• A test can miss real hardware damage if it checks only digital toggle behavior without checking voltage-level quality or waveform margin.
• Strong quality improvement needs both generation-prevention actions and screening-improvement actions.
• Statistical validation is useful when proving that countermeasures reduced confirmed defect rate.